(1) Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a method of forming a split-gate flash memory cell having a spacer like floating gate.
(2) Description of the Related Art
With the ever increasing demand for miniaturization of semiconductor devices, it is becoming more and more necessary to scale down every possible component of the devices. A split-gate flash memory, by its very nature of being split up where the floating gate somewhat overlaps the control gate, is larger in size than a stacked-gate cell. However, as it is explained more in detail below, the split-gate has operational advantages over the stacked cell. Hence, it is desirable to keep the split-gate characteristics while shrinking the size of its components, such as the floating gate and the control gate. It is disclosed later in the embodiments of the present invention a method of fitting the floating gate as a spacer underlying the control gate so as to affect more shrinkage in size than possible through conventional means.
Over the years, numerous improvements in the performance as well as in the size of memory devices have been made by varying the simple, basic one-transistor memory cell, which contains one transistor and one capacitor. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. In general, memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1a. Here, two MOS transistors share a source (25). Each transistor is formed on a semiconductor substrate (10) having a first doped region (20), a second doped region (25), a channel region (23), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (23) have a first conductivity type, and the first (20) and second (25) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1a, the first doped region, (20), lies within the substrate. The second doped region, (25), also lies within substrate (10) and is spaced apart form the first doped region (20). Channel region (23) lies within substrate (10) and between first (20) and second (25) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween, which in turn is formed over polyoxide cap (45).
Prior art contains many different ways of forming split-gate type transistor devices. Fukase in U.S. Pat. No. 5,989,960 shows such a device and the making of the same where the transistor has a substrate, and a floating gate electrode is located on the substrate. A control gate electrode is provided having thick and thin film sections over the floating electrode. As source region and a drain region are formed separately in the substrate. The thin film section is formed partially over the drain region and impurity is passed into the substrate through the thin film section to form the drain region.
A different split-gate flash memory cell is disclosed by Yang in U.S. Pat. No. 6,093,945 where an outwardly-diverging control gate is stacked on but separated form a pair of opposing floating gates via an inter-poly dielectric layer. The split-gate flash memory is formed by (a) forming a first dielectric layer having a trench region on a substrate; (b) forming a tunnel oxide layer in the trench region; (c) forming a first polysilicon layer covering the first dielectric layer and the tunnel oxide layer; (d) applying an an isotropic etching technique on the first polysilicon layer to form a pair of opposing polysilicon sidewall spacers on the sidewalls which will eventually become floating gates; (e) depositing an inter-poly dielectric layer on the polysilicon sidewall spacers and the tunnel oxide layer; (f) filling the channel area between the pair of polysilicon sidewall spacers with a second polysilicon layer; (g) planarizing the second polysilicon layer so that relative to the first dielectric layer to form a control gate; (h) removing the first dielectric layer, capping the control gate and the floating gate with a final oxide layer, and forming source and drain regions in the substrate using ion implantation. The split-gate flash memory eliminates the over-erase problem experienced with the self-aligned ETOX flash memory cells, while allowing its cell dimension to maintain at least the same using the conventional photolithography technique.
Ahn of U.S. Pat. No. 5,612,237 discloses still another method of making a flash memory cell in accordance with the following process steps: forming a oxide film on a portion of the silicon substrate by means of the LOCOS process using the patterned nitride film as an oxidation preventing layer; dry-etching a portion of the oxide film using the patterned nitride film as the etching mask; forming a tunnel oxide film, forming floating gates of a symmetric structure at the etched face: removing the patterned nitride film; forming source and drain regions by means of the self-aligned ion implantation method using the residual oxide film remaining below the patterned nitride film and the floating gates; removing the residual oxide film; forming a select channel region at this portion by means of the ion implantation process for controlling a threshold voltage; and then forming an interpoly oxide film and a control gate by means of the common processes.
A method of forming a dynamic random access memory (DRAM) cell is shown in U.S. Pat. No. 6,054,345 by Alsmeier, et al. Here, the cell includes a substrate, a transfer gate overlying the substrate, a storage device coupled to the transfer gate, a deep depleted region formed in the substrate under the storage means, and a bit line for initially receiving the charge and the substrate receiving the charge via the transfer gate. A process for making the same device includes depositing a first gate oxide over a substrate having a trench and depositing a nitride over the first gate oxide, forming openings in the nitride down to the gate oxide, and depositing polysilicon over the nitride and etching first spacers in the polysilicon along the sidewalls of the openings in the nitride. A second polysilicon material is deposited over the first spacers and substrate and second spacers are formed in the second polysilicon material. A contact window is opened between first and second ones of the first spacers and a highly doped polysilicon is deposited in the contact window. A contact is formed over the highly doped polysilicon.
Forming of very small structural widths using spacers is further described by Kerber in U.S. Pat. No. 6,027,972, according to which: a first layer deposited over an edge of a structure is anisotropically etched back; spacer at the edge of the structure which remains after the first layer and the structure are removed, after further deposition and etching steps, finally defines the position and width of the resulting microstructure.
While prior art offers different approaches for forming different split-gate flash memory cells, the present invention discloses, later in the embodiments of the present invention, still a different method of forming spacer-like floating gates which have their own control gates, unlike U.S. Pat. Nos. 6,093,945 and 5,612,237 cited above, and which are storage gates, unlike U.S. Pat. No. 5,989,960, and are for an EEPROM, unlike in U.S. Pat. No. 6,054,345, which are for a DRAM, and keep these spacer-like structures rather than removing them as in U.S. Pat. No. 6,027,972. The spacer process of the instant invention is also different from that of U.S. Pat. No. 6,051,470, because the spacer gate of the latter is not a floating gate. Also, the instant spacer floating gates are not cylindrical as that of U.S. Pat. No. 6,103,575.
It is therefore an object of this invention to provide a method of forming a split-gate flash memory cell with spacer-like floating gates.
It is another object of this invention to provide a method of forming split-gate flash memory by using a spacer technology.
It is still another object of the present invention to provide a method of shrinking the size of a split-gate flash memory cell through the use of a spacer technology.
It is yet another object of the present invention to provide a split-gate flash memory with two independent cells having spacer-like floating gates and control gates which provide tunneling and which share the same source.
These objects are accomplished by providing a substrate; forming a structure layer over said substrate; defining a floating area in said structure layer; forming an opening for said floating area in said structure layer; forming a tunnel oxide at the bottom of said opening; forming a floating material over said substrate, including said opening; forming floating spacers along the vertical sides of said opening; removing said structure layer; performing a source implant; forming an oxide layer over said floating spacers; forming a controlling material over said oxide layer; and etching said controlling material and said oxide layer to complete the forming of said split-gate of this invention having a spacer-like floating gate.
These objects are further accomplished by providing a substrate having active and field areas defined; a source and drain regions in said active area; floating spacers formed over and separated from said source region with a tunnel oxide; an intergate oxide layer formed over said floating spacers; and controlling layers formed over said intergate oxide layer sharing the same said source region.